The Great Margin Relocation

Hyperscalers are building their own AI chips to escape Nvidia — but the money they save lands on Broadcom, TSMC and the memory makers

The Ecliptic · Issue No. 002 · July 23, 2026

~75%

Nvidia's gross margin — the toll every merchant-GPU buyer pays

27.8%

ASIC share of 2026 AI-server accelerator shipments; passes GPUs by 2027–28

44–50%

lower total cost of ownership on captive workloads (Ironwood, Trainium3)

~95%

of custom AI-ASIC co-design captured by Broadcom and Marvell

The driver

Hyperscalers are attacking the one number that defines Nvidia

Illustrative, indexed to a merchant Nvidia system = 100. The ~44% (Ironwood vs GB200) and ~50% (Trainium3 vs Blackwell NVL72) figures are vendor and analyst total-cost-of-ownership claims cited in the cover report, not independent measurements.

The binding driver of the custom-silicon wave isn't a better chip. It's Nvidia's margin — and its largest customers have decided to keep that margin for themselves.

Nvidia still ships an estimated 80–92% of AI accelerators and books a gross margin near 75% — the toll every merchant-GPU buyer pays on top of the silicon's build cost.
A hyperscaler running one enormous, fixed workload can design a chip that does only what it needs, buy fabrication at cost-plus, and pocket the difference: vendors and analysts cite ~44% lower TCO for Google's Ironwood vs a GB200 and ~50% for AWS Trainium3 vs Blackwell NVL72; Anthropic reports up to 50% off training and inference on Trainium.
The share is moving fast — ASICs are on track for 27.8% of AI-server accelerator shipments in 2026 and to overtake merchant GPUs on unit volume by 2027–2028.

The relocation

The margin doesn't die — it moves down the stack

Read as "the end of Nvidia's monopoly," the story is usually wrong. The ~75% doesn't vanish when a hyperscaler builds its own chip; a durable slice simply relocates to the enablers underneath.

The high-quality annuity shifts to the merchant co-design layer: Broadcom and Marvell together shape ~95% of custom AI ASICs, and Broadcom's AI-semiconductor revenue hit $10.8B in a single quarter, up 143%.
Below them sits the real chokepoint — TSMC advanced packaging and HBM memory — that every accelerator, custom or merchant, must pass through (the same constraint Parameter maps in this issue's memory-chokepoint feature).
The cleanest expression of the thesis, in our view, is therefore long the enabler layer, not short Nvidia.

The verdict

Sovereignty, or just a change of masters?

Custom silicon is sold as independence. On the numbers, it entrenches the incumbents rather than democratising compute.

It swaps CUDA lock-in for a captive software stack (JAX, PyTorch/vLLM, Triton) and the very same TSMC-and-HBM dependency that constrains everyone else.
A leading-edge program only pencils at hyperscaler workload volume — so the tool belongs to the five largest buyers, not to new entrants.
Our base case: the wave is best read as a Broadcom-and-TSMC trade, and it keeps the club closed.

The Ecliptic, Issue No. 002, cover analysis, drawn from Parameter flagship PAR-0006 (July 23, 2026) and its cited sources. The chart is an illustrative TCO index, not a measured series.